This application claims priority to Korean Patent Application No. 2005-49305, filed on Jun. 9, 2005 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to controlling impedance at an I/O (input/out) pad of a semiconductor device, and more particularly to more accurately matching such impedance to an external impedance.
2. Description of the Related Art
Generally, semiconductor devices such as a microprocessor, a field-programmable gate array (FPGA), a controller and a memory device are mounted on a printed circuit board (PCB) for forming an electronic system. Each semiconductor device is coupled to at least one other semiconductor device through a transmission line, such as a PCB wire.
For data transmission with preserved signal integrity, impedance matching is desired between an I/O (input/output) pin of the semiconductor device and the transmission line. With increased operating speed, signal amplitude in the semiconductor device has been decreasing such that such impedance matching is even more important.
FIG. 1 shows a block diagram of a conventional impedance controller as disclosed in Korean Patent Laid-Open Publication No. 2003-96564. The impedance controller 26 includes PMOSFETs (P-channel metal oxide semiconductor field effect transistors) P1 and P2.
The PMOSFET P1 is coupled to a pull-up control path for controlling a pull-up transistor group of an output buffer, and the PMOSFET P2 is coupled to a pull-down control path for controlling a pull-down transistor group in the output buffer. The PMOSFET P1 has a source coupled to a power voltage VDDQ and a drain coupled to a ZQ terminal. VDDQ is equal to a power voltage for driving the output buffer.
The pull-up control path includes a PMOS array 102, an operational amplifier 103, an up/down counter 104, a dithering detector 105, a register 106, a clock generator 107, and a transmitter 108. The pull-down path includes an NMOSFET array 110, an operational amplifier 111, an up/down counter 112, a dithering detector 113, and a register 114.
A reference voltage generator (not shown in FIG. 1) generates a reference voltage VREF that is about VDDQ/2 for being applied on a negative input terminal of an operational amplifier 101 having an output for controlling the PMOSFET P1. A drain voltage VZQ of the PMOSFET P1 at the ZQ terminal is fed-back on a negative input terminal of the operational amplifier 101. Consequently, VZQ becomes substantially equal to the reference voltage VREF.
The reference voltage VREF is applied on a positive input terminal of the operational amplifier 103 having a negative input terminal coupled to a linkage node REFU between the drain of the PMOSFET P1 and the PMOS array 102. The up/down counter 104 generates a code (i.e., data bits U0 through Un−1) in response to an output UOUT of the operational amplifier 103. Each of n dummy transistors in the PMOS array 102 is turned on or off selectively depending on the data bits U0 through Un−. Consequently, a voltage at the linkage node REFU becomes substantially equal to the reference voltage VREF.
The PMOS array 102 includes n PMOSFETs having sources coupled to the power voltage VDDQ and having drains coupled to the linkage node REFU. Each gate of the n PMOSFETs is turned on or off by a respective one of the data bits U0 through Un−.
The dithering detector 105 receives the output UOUT of the operational amplifier 103 to activate a detection signal UDET when a predetermined condition is satisfied. Referring to FIG. 2, the dithering detector 105 activates the detection signal UDET with a high level when the output UOUT of the operational amplifier 103 is an alternating value of ‘1, 0, 1, 0, 1’.
The register 106 stores the data bits U0 through Un−1 provided from the up/down counter 104 when the dithering detector activates the detection signal UDET. The data bits U0 through Un−1 stored in the register 106 are transmitted to the output buffer through the transmitter 108.
The clock generator 107 generates a clock signal UP_CK that is used in the up/down counter 104 and the dithering detector 105, and a clock signal DN_CK that is used in the up/down counter 112 and the dithering detector 113 in the pull-down control path that operates in a similar manner as the pull-up control path.
The conventional impedance controller selectively turns on or off a plurality of transistors for matching an impedance of the output buffer to a reference impedance. Such matching is indicated by detecting an alternating bit pattern ‘1, 0, 1, 0, 1’ from the output of the operational amplifier 103 or 111.
This method is also disclosed in Korean Patent Laid-Open Publication No. 2003-13983.
However, when the output impedance is precisely equal to the reference impedance in the conventional impedance controller, the output of the operational amplifier 103 or 111 may have an undesired bit pattern such as ‘1, 1, 0, 0, 1, 1, 0, 0’, resulting in improper operation of the impedance controller. Furthermore, multiple codes may cause dithering in the conventional impedance controller. However, the conventional impedance controller selects just an arbitrary one of such codes to be transmitted without any regard to which of such codes results in better impedance matching.